Equipment and Facilities

Our laboratory is equipped with a state-of-the-art fully automated wafer probe station, enabling high-precision DC, RF, and mixed-signal characterization of advanced semiconductor devices and integrated circuits at the wafer level. The system is built around the TS2000-IFE Automated Probe System from MPI Corporation, providing a robust and flexible platform for both academic research and industry-relevant testing.

The probe station supports up to 200 mm wafers and individual die measurements, with automated wafer handling, fine chuck alignment (X-Y-θ), and precise Z-control for repeatable and damage-free probing.

For electrical characterization, the system is configured with triaxial, coaxial, Kelvin, and RF probe arms, enabling ultra-low-leakage DC measurements as well as high-frequency RF and microwave testing. The guarded chuck architecture minimizes parasitic capacitance and leakage, making the setup ideal for advanced CMOS, RFIC, mixed-signal, and emerging device technologies. High-resolution programmable microscope stages and digital imaging provide accurate probe placement and detailed visual inspection during testing.

The entire platform is controlled through MPI’s SENTIO® software suite, supporting automated test sequences, instrument control (including SMUs, VNAs, and parameter analyzers), and seamless data acquisition. This enables reproducible experiments ranging from device-level characterization to full wafer mapping, making the system well suited for research in analog/RF ICs, neuromorphic hardware, sensors, and next-generation semiconductor technologies.

Together, this infrastructure allows our lab to perform industry-grade wafer-level measurements, bridging the gap between fabrication and system-level validation and supporting both exploratory research and tape-out-ready characterization workflows.

Our lab features a high-performance real-time oscilloscope from Keysight Technologies, enabling precise time-domain analysis of high-speed electrical signals. With 6 GHz analog bandwidth, up to 16 GSa/s sampling, and 8 fully synchronized channels, the system supports detailed investigation of fast transients, clock integrity, jitter, and multi-lane high-speed interfaces.

The large acquisition memory and advanced triggering capabilities allow long-record captures without sacrificing time resolution, making the oscilloscope well suited for mixed-signal IC validation, high-speed serial links, power integrity analysis, and transient characterization of RF and analog front-ends. This capability is essential for correlating time-domain behavior with frequency-domain and system-level performance.

For frequency-domain measurements, the lab is equipped with a compact, high-accuracy 4-port vector network analyzer (VNA) covering 9 kHz to 20 GHz. This system enables full S-parameter characterization of passive and active RF components, including on-wafer devices, packaged ICs, antennas, filters, and interconnects.

The multi-port capability supports differential measurements, multi-port de-embedding, and advanced calibration workflows, making it ideal for RFIC and microwave research. Combined with wafer-level probing, the VNA allows direct extraction of small-signal models and verification of RF performance across a broad frequency range.

The laboratory also includes a wideband vector signal generator capable of producing spectrally pure signals from 100 kHz up to 12 GHz. This platform supports continuous-wave (CW), pulsed, and digitally modulated waveforms, enabling realistic excitation of RF and mm-wave systems.

With excellent phase noise performance and flexible modulation options, the signal generator is well suited for receiver characterization, transmitter testing, phase-noise-sensitive experiments, and system-level validation of RFICs and mixed-signal architectures. It plays a central role in closed-loop measurement setups when combined with the VNA, oscilloscope, and wafer-probe infrastructure.

Our laboratory is equipped with a high-performance signal and spectrum analyzer from Rohde & Schwarz, enabling precise frequency-domain and time-domain analysis of RF and microwave signals. The FSVA3000 series analyzer provides coverage from 10 Hz to 13.6 GHz, supporting a broad range of measurements relevant to modern wireless, RFIC, and mixed-signal research.

The system offers low phase noise, high dynamic range, and fast sweep speeds, making it well suited for characterizing spectral purity, spurious emissions, harmonics, and noise performance of oscillators, transmitters, and RF front-ends. With an integrated RF preamplifier and high-stability OCXO reference, the analyzer enables accurate low-level signal measurements and repeatable results across long measurement sessions.

Advanced digital signal analysis capabilities, including wide analysis bandwidth (up to 200 MHz) and enhanced processing power, allow in-depth evaluation of modulated signals, transient RF behavior, and wideband communication waveforms. The large touchscreen display and intuitive user interface support efficient interactive debugging as well as scripted and automated measurements.

This instrument plays a critical role in our lab’s RF characterization workflow, complementing vector signal generation, vector network analysis, and high-speed time-domain measurements. Together, these capabilities enable comprehensive validation of RFICs, mixed-signal systems, and emerging wireless and sensing technologies at both the device and system levels

What it is: An evaluation kit tailored for embedded vision—great for surveillance, ADAS, machine vision, AR, drones, and medical imaging.

Why it’s powerful: Built on the ZU7EV MPSoC, combining CPUs, GPU, hardware video codec, and FPGA fabric on one chip for real-time, low-latency processing.

Key specs: • Quad Arm Cortex-A53 (applications) + Dual Cortex-R5 (real-time) • Mali-400 MP2 GPU • Hardware H.264/H.265 codec up to 4K@60fps • 16nm FinFET+ programmable logic for custom acceleration • Rich peripherals/interfaces for vision sensors and I/O

Summary: A one-board platform to prototype and deploy high-performance, low-power vision AI at the edge.

What it is: Flagship Versal AI Core (VC1902) evaluation kit for ultra-high-throughput AI inference and signal processing from cloud to edge.

Why it stands out • Up to 100× compute vs. server-class CPUs (targeted workloads) • 400 AI Engines + 1,968 DSP Engines • Dual-core Arm® Cortex-A72 (apps) + Dual-core Cortex-R5F (real-time) • ~1.97M logic cells (~900k LUTs), 28 programmable NoC ports • 4 integrated memory controllers, 770 max I/O pins

Use cases: Data-center acceleration, 5G/DFE, cable-access head-end, wireless test, ADAS/automotive, A&D radar/early warning.

Summary: A reconfigurable, AI-engine–powered platform delivering the Versal portfolio’s highest AI/DSP throughput for cloud, network, and edge solutions.

What it is: A compact evaluation board for rapid embedded-system prototyping using Zynq-7000 SoCs (CPU + FPGA on one chip).

Why it stands out • Ships with reference designs, IP, and tools for fast bring-up • Demonstrates an embedded video pipeline out of the box • 1 GB DDR3 component memory for applications and buffering • Dual Arm® Cortex-A9 processors plus programmable logic for acceleration

Use cases: Embedded vision, industrial control, networking prototypes, and edge compute demos where a CPU+FPGA platform accelerates real-time tasks.

Summary: All-in-one CPU+FPGA (Zynq-7000) board for fast embedded prototypes—dual Cortex-A9, 1 GB DDR3, Ethernet/HDMI/FMC—ideal for quick bring-up of vision, control, and edge applications.

What it is: A 40 Gb/s connectivity and prototyping platform based on the Virtex-7 VX690T FPGA, built for high-bandwidth networking and serial-I/O designs.

Why it stands out • Turnkey bring-up with reference designs, IP, and tools • 10GBASE-R demo to external DDR3 • Dual 4 GB DDR3 SODIMMs (up to 933 MHz / 1866 Mb/s) • Rich high-speed I/O: PCIe Gen3 x8, 4× SFP/SFP+, SMA, UART • FMC mezzanine expansion • Supports MicroBlaze soft 32-bit RISC for embedded control

Device highlights (XC7VX690T-2FFG1761C) • ~693k logic cells • 3,600 DSP slices • ~52.9 Mb on-chip memory (52,920 Kb) • 80 GTH transceivers @ 13.1 Gb/s • 1,000 I/O pins

Use cases: 10/40 GbE packet processing, high-speed serial protocol development, storage/networking accelerators, and lab test equipment.

What it is: An RFSoC-based evaluation kit for rapid 5G/RF system prototyping—ideal for massive-MIMO radios, IF transceivers, radar, satcom, and RF test gear.

Why it stands out • Comes with integrated RF design examples • Add-on cards for fast bring-up & measurement: o XM650 16T16R N79 loopback card (quick loopback tests) o XM655 16T16R breakout card (in-depth performance measurements) o CLK104 RF clock card: internal up to 1.2 GHz, external up to 10 GHz reference clocking

Target applications • 5G sub-6 GHz massive-MIMO • 5G mmWave IF transceivers • Fixed wireless access • Digital phased-array radar • Terrestrial satellite communications • Spectrum analyzers & high-speed RF testers

Summary: A ready-to-measure RF lab on a board—memory, clocks, and I/O tuned for building and validating high-throughput 5G/RF systems fast.

The DE1-SoC is an Intel/Altera development board built around the Cyclone V SoC (5CSEMA5F31C6), combining an FPGA fabric with a dual-core ARM Cortex-A9 Hard Processor System (HPS). This heterogeneous architecture supports everything from basic digital logic labs to multimedia and embedded Linux projects, with about 85K logic elements, 4,450 Kbits of on-chip memory, multiple PLLs, and hard memory controllers for high-performance designs.

For development and storage, the board includes an EPCS128 configuration device, an on-board USB Blaster II for programming/debug, 64 MB SDRAM connected to the FPGA, 1 GB DDR3 for the HPS, and a microSD card socket for OS/images. It also provides rich I/O and peripherals: Gigabit Ethernet, USB 2.0 host ports, UART-to-USB, PS/2, IR, and multiple expansion options including two 40-pin 3.3V headers, a 10-pin ADC header, and an LTC connector exposing SPI, I²C, and GPIO.

The board is well suited for signal acquisition and multimedia projects thanks to a 24-bit VGA DAC, a 24-bit audio CODEC (line-in/line-out/mic), and a TV decoder with composite TV-in. It also features an 8-channel, 12-bit ADC (500 KSPS, 0–4.096 V), user I/O (keys, switches, LEDs, six 7-segment displays), an onboard G-sensor, and is powered via a 12 V DC input.

BRICCS has Intel's most advanced 2nd generation neuromorphic chip, called Loihi-2. It is an event-driven research processor, designed to execute general SNN architectures for vision/audio/signal/text processing tasks. It supports more than 1 million spiking neurons and is asynchronous in design. Across a variety of SNN workloads, Loihi-2 consumes far less than 1 watt of power, compared to the tens to hundreds of watts on standard CPUs/GPUs [1]. When idle and always-on case, it consumes 30-80 mW, and its dynamic power per core (when active) is 0.3-8 mW [2]. The Loihi-2 chip also comes with 6 x86 low-power Lakemont processors to execute INT32 bit operations, apart from the 128 Neuro-Cores to execute SNNs. Our group has developed a few wireless applications on Loihi-2, e.g., spectrum sensing, jamming detection, etc. - with energy gains of more than 100-500 times compared to the CPUs. We are currently building a drone detection system on Loihi-2, with plans to use it for robotics applications as well. This chip is best suited for edge applications, as well as for large scale neuromorphic applications, e.g., the Hala Point system is composed of 1152 Loihi-2 processors, with support for more than 1 billion neurons and 128 billion synapses [3].

BRICCS offers a neuromorphic dynamic vision System on Chip (SoC) with integrated sensing and compute made possible with Dynamic Vision Sensor (DVS) and processor. It is fully asynchronous with no global clock signal and an always on profile (no wake-up procedures) with a resting power of 0.42 mW.

The kit comes with a complete software toolchain, including data management, model simulation and host management.

Our group is currently performing algorithmic and application-specific benchmarking by exploring different classes of Spiking Neural Network workloads across a variety of network architectures to determine performance metrics such as latency, throughput, and power.

The low power capability of this neuromorphic chip can be beneficial for edge devices that span a range of research applications, including but not limited to wearable health monitoring devices, autonomous vehicle sensors, and other IoT applications.

Xylo Audio 3 is a low-power neuromorphic processing platform developed by SynSense AG, designed for event-driven signal processing using Spiking Neural Networks (SNNs). The platform is optimized for temporal and rate-based encoding of continuous-time signals and supports fully asynchronous computation without a global clock, enabling ultra-low power operation suitable for always-on sensing applications.

The XYLO Audio 3 Development Kit consists of an Xylo neuromorphic processor daughterboard mounted on an FPGA-based motherboard, which provides flexible interfacing, data streaming, and host communication. The system is primarily intended for real-time processing of temporal signals such as audio streams, sensor-derived time series, and other continuous biological or physical signals that can be encoded into spike trains.

Our group uses the XYLO Audio 3 platform to explore event-based representations and regime-change detection in slow biological and chemical processes, including growth dynamics, metabolic activity proxies, and longitudinal biosensing signals. Rather than focusing on high-precision numerical inference, the emphasis is on detecting state transitions, temporal patterns, and dynamic responses under constrained power budgets.

The energy-efficient and event-driven nature of the Xylo architecture makes it well suited for edge intelligence applications where continuous monitoring, low latency response, and minimal power consumption are critical. Representative application domains include biosignal monitoring, liquid biopsy signal preprocessing, adaptive laboratory instrumentation, and embedded decision modules for portable sensing devices.

The Tello is a compact, lightweight quadcopter (about 80 g with propellers and battery) measuring 98 × 92.5 × 41 mm and using 3-inch propellers, making it easy to carry and fly indoors or outdoors in calm conditions. It includes a vision system, range finder, barometer, LED, and 2.4 GHz 802.11n Wi-Fi, and supports 720p live view; charging is via a micro-USB port.

In flight, Tello can reach up to 100 m range, 8 m/s top speed, about 13 minutes of flight time, and a maximum height of 30 m, powered by a detachable 1.1 Ah / 3.8 V battery. Its camera captures 5 MP photos (2592 × 1936) and HD 720p/30 fps video with an 82.6° field of view, saving media as JPG and MP4, and it includes electronic image stabilization (EIS) for smoother footage.

The DE10-Nano Self-Balancing Robot Development Kit is a hands-on platform built around the Terasic DE10-Nano (Intel Cyclone V SoC FPGA) that demonstrates how FPGA logic can create application-tailored I/O and real-time control. The robot uses the board’s on-board accelerometer (and a 6-axis MEMS motion sensor on the motor driver board) to maintain balance, while FPGA/HPS resources integrate motor control and multiple sensing/communication functions such as ultrasonic distance measurement, IR detection, and Bluetooth/Wi-Fi connectivity. With an optional camera add-on and an FPGA design developed using the license-free Intel HLS compiler, the kit can also perform color-based object tracking and following, making it ideal for customization and experimentation.

On the compute side, the HPS provides an 800 MHz dual-core Arm Cortex-A9, 1 GB DDR3, Gigabit Ethernet, USB OTG, and microSD storage, plus UART-to-USB and reset/user controls. The FPGA fabric (Cyclone V SE 5CSEBA6U23I7, ~110K LEs) supports expansion and prototyping through dual 40-pin headers, an Arduino Uno R3–compatible header, and an analog input header with an SPI A/D converter, along with onboard programming via USB-Blaster II and video output via HDMI TX. The included motor driver board adds DC motor drivers and connectors, IR receiver, ultrasonic interface, power monitoring, and regulated power distribution (12 V input, 5 V output to the FPGA board) to complete a robust robotics development stack.

The A-Cute Car is an FPGA-based three-wheeled robotic car kit. This car can provide higher operation performance than the MCU based robotic car, because the FPGA provides more powerful computing power than the MCU.

The car is driven by two DC motors. It can move in any direction, by changing the speed and direction of each wheel by changing the speed and direction of the two DC motors. The car is equipped with a sensor board which contains seven line tracking sensors by implementing the line following function. The car also contains a power convert system so the car can be driven by 3.3V~12V battery pack. The car contains an IR receiver so that the car can be remotely controlled with the IR controller included in the car kit. Buzzers and lamps are equipped just for fun.

The car contains a 2x20 GPIO expansion header and a 2x6 TMD expansion header. The 2x6 TMD expansion header can be expanded with the Terasic Bluetooth module BTS-TMD, so the car can be remotely controlled with a Bluetooth device, e.g. Android Cell Phone. Besides the hardware, the car kit also includes open source examples. Based on the example codes, developers can quickly implement their application designs.