Virginia Tech® home

BRICC Openings

1. PhD position in Physical Design of Integrated Circuits (ICs)

Fall 2025 intake

Date: Oct, 2024

We are seeking a highly motivated PhD student for research in Physical Design of Integrated Circuits (ICs), focusing on nanometer-scale technologies. The project involves:

  1. Floorplanning, placement, routing, and clock tree synthesis.
  2. Power, performance, and area (PPA) optimization.
  3. Advanced techniques for managing delay, leakage, and parasitics.
  4. Use of leading EDA tools like Cadence Innovus for design, verification, and tapeout.
Preference will be given to candidates with industry experience in chip tapeouts.

Qualifications:

  1. Bachelor degree in Computer/Electrical Engineering or related fields.
  2. Experience with physical design tools (e.g., Innovus, Synopsys ICC).
  3. Proficiency in Tcl, Python, Verilog, or VHDL.
  4. Industry experience in chip tapeouts is preferred.

How to Apply:

Submit your CV, transcripts, and references to: Prof. Yang (Cindy) Yi.

NOTE: Please include detailed information in the CV such as industrial work experience, a list of publications (including submitted or ongoing), IELTS and GRE scores (or intended dates to take the exams).

2. PhD position in Spiking Neural Networks

Fall 2025 intake

Date: Nov, 2024

We are seeking a highly motivated PhD student for research in Spiking Neural Networks (SNNs), focusing on On-chip training, deployment, and application of SNNs on Intel’s Loihi-2 neuromorphic chip (present on-site in BRICC Lab). The research in SNNs at the BRICC lab entails the following (but not limited to):

  1. Development of reservoir-based spiking time-series processing models.
  2. R-STDP based On-chip training of SNNs and their evaluation on the Loihi-2 neuromorphic chip using Lava library.
  3. Application of developed spiking models for wireless communication projects, agriculture projects, neuroscience projects, etc.
  4. Developing novel training methodologies to improve the training-efficiency and accuracy of large scale SNNs on GPUs.
Preference will be given to the candidates who already have the related SNN research experience in their Bachelor’s or Master’s. Experience with Loihi-1 or Loihi-2 will be an added advantage

Qualifications:

  1. Bachelor’s/Master's degree in Computer/Electrical engineering or related fields.
  2. Proficiency in Python programming, with experience of building Deep Learning models via PyTorch/Tensorflow.
  3. Experience of authoring research papers (in Deep Learning or SNN domain) as first/second author is a plus.
  4. The student should be passionate & self-motivated, and be comfortable in working in collaborative settings.

How to Apply:

Email your CV, transcripts, and references to Prof. Yang (Cindy) Yi. Make sure to mention your publications (including submitted or ongoing) in your CV. Also mention your GRE scores if applicable.

NOTE: We have a physical Loihi-2 board on-site in the BRICC Lab. Aslo, the BRICC lab will be moving to the Innovation Campus (of Virginia Tech) near Washington DC in the Fall of 2025. This position is funded: Funding for the first year is usually covered by Graduate Teaching Assistantship, the following years are covered by Graduate Research Assistantship (based on satisfactory progress).

3. PhD position in Field Programmable Logic Array (FPGA) Design

Fall 2025 intake

Date: Nov, 2024

We are seeking a highly motivated PhD student for research in FPGA design, focusing on IP integration, architecture development with RTL or HLS language, and Verification. The research in FPGA design at the BRICC lab entails the following:
  1. Architecture design for different Artificial Intelligence based accelerators
  2. Efficient micro-architecture design using SystemVerilog/ Verilog or C/C++ using HLS
  3. IP integration on RTL code and IP-integrator level
  4. On-board CPU usage for HW/SW co-design
  5. Knowledge of Timing closure requirements to deliver complex System-On-Chip designs
  6. On-board FPGA implementation using UART, ETHERNET-PHY, or other communication protocols such as SPI, I2C
  7. State-of-the-art testbench verification using SystemVerilog
  8. Application of the ML model to different domains such as wireless, physical routing or any other applications, etc.

Preference will be given to the candidates who already have some of the above FPGA experience in their Bachelor’s or Master’s. Experience with High-level Synthesis (HLS) or FPGA on-board testing will be an added advantage.

Minimum Qualifications:

  1. Bachelor’s/Master's degree in Computer/Electrical engineering or related fields.
  2. Experience with FPGA or any RTL design tools (e.g., Vivado/Quartus).
  3. Proficiency in Verilog, Python, and/or C/C++(for HLS).
  4. Experience in the design and verification of complex digital system design on advanced FPGA boards is preferred.

Applicants will also be preferable if they have some related experience/knowledge in the following fields:
  1. Experience in UVM/TLM/Scorecard/Environment and testing/verification
  2. Knowledge of Clock domain Crossing
  3. Machine learning experience using sci-kit learn, TensorFlow, PyTorch

How to Apply:

Email your CV, transcripts, and references to Prof. Yang (Cindy) Yi. If you have any publications, kindly mention them in your CV (including submitted or ongoing).